| dc.contributor.author | Shansky, David | en_US |
| dc.date.accessioned | 2009-06-12T22:14:39Z | |
| dc.date.available | 2009-06-12T22:14:39Z | |
| dc.date.issued | 1954-07-13 | en_US |
| dc.identifier | MC665_r13_M-2904 | en_US |
| dc.identifier.uri | http://hdl.handle.net/1721.3/40366 | |
| dc.description.abstract | A significant reduction of the cathode count coupled with an increase in operating speed of the FSQ-7 Memory banks can be achieved by a redesign of some of the sections of Memory. In order of increasing difficulty these are: the Digit Plan Drivers, the Sense Amplifiers, and the address selection system. Approximately 6 man-months of engineering time would be required to effect these changes. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | Lincoln Laboratory - Division 6 | en_US |
| dc.relation.ispartofseries | Project Whirlwind Memo M-2904 | en_US |
| dc.relation.ispartofseries | Project Whirlwind Collection, MC665 | en_US |
| dc.title | Proposed Changes in FSQ-7 Memory | en_US |
| dc.type | Technical Report | en_US |
