| dc.contributor.author | Crane, J. D. | en_US |
| dc.date.accessioned | 2009-06-15T19:34:04Z | |
| dc.date.available | 2009-06-15T19:34:04Z | |
| dc.date.issued | 1955-08-25 | en_US |
| dc.identifier | MC665_r15_M-3853 | en_US |
| dc.identifier.uri | http://hdl.handle.net/1721.3/40492 | |
| dc.description | Includes: introduction; equipment and logical functions submitted for acceptance; results of acceptance test demonstrations; XD-1 performance during June 1955; distribution of failures in XD-1; margins and margin history; summary; and tables. | en_US |
| dc.description.abstract | Memorandum disseminating the results of a system test performed on the central computer portion of the AN/FSQ-7 during the month of June 1955. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | Lincoln Laboratory - Division 6 | en_US |
| dc.relation.ispartofseries | Division 6 Memo M-3853 | en_US |
| dc.relation.ispartofseries | Project Whirlwind Collection, MC665 | en_US |
| dc.subject.other | computer reliability | en_US |
| dc.subject.other | precision resistors | en_US |
| dc.subject.other | core memory circuits | en_US |
| dc.subject.other | card machine | en_US |
| dc.subject.other | voltage margins | en_US |
| dc.title | Results of the system test performed on the AN/FSQ-7 (XD-1) during June 1955 | en_US |
| dc.type | Technical Report | en_US |
