Multi-Coordinate Selection Systems for Magnetic-Core Storage

Abstract

For many computational applications there is a need for a high-speed digital computer with a large internal memory capacity. The search for a reliable random-access memory with a fast information-access time brought about the development of the magnetic-core memory system. Systems of this type using a 2-coordinate "read" and a 3-coordinate "write" have been operating very successfully for some time. This thesis report reviews and extends the theory of magnetic-core memories for the generalized n-coordinate selection system. The criteria for obtaining the maximum selection ratio under a variety of conditions and arrangements are derived, and the resultant effects on the noise and sensing problems are discussed. A particular system which use a 4-coordinate read and 5-coordinate write in an attempt to reduce the number of required electronic circuits is analyzed. Experimental work with the breadboard of such a system (using a 3-to-2 selection-current ratio) was performed. The results, here indicated, show that a 4096-bit digit plane (8 driving lines in each of the 4 coordinates) is operable, albeit with very narrow margins, with a memory cycle time of approximately 9 microseconds, and with no more than one-fourth the number of driving cathodes required by a comparable system which uses a 2-coordinate read and a 3-coordinate write. The recent development of improved cores and diodes satisfactory for low-level mixing of memory signals could be used to improve the operating margins significantly. Because it present information of general interest, this thesis report, which has had only very limited distribution, is being issued as a Division 6 R-Series Report.