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dc.contributor.authorHughes, A. D.en_US
dc.date.accessioned2009-05-09T05:09:54Z
dc.date.available2009-05-09T05:09:54Z
dc.date.issued1953-06-16en_US
dc.identifierMC665_r06_M-2219.pdfen_US
dc.identifier.urihttp://hdl.handle.net/1721.3/39482
dc.description.abstractThe 32 x 32 magnetic-core memory planes for MTC were constructed from cores tested and sorted on a production basis. To obviate the possibility of defective cores, each core was retested after it had been wired into a memory plane. A device was constructed to enable the operator to send current pulses through each core in a plane and observe output. The necessary test equipment was arranged to provide the pulses and allow measurement of the outputs. No defective cores were found. The test showed that the limits of output voltages at the sensing time used were +17%. Five cores with outputs outside of these limits were replaced. Taking into account that the variable factors inherent in testing and equipment are ±5%, the cores in each plane are within approximately ±20% limits.en_US
dc.language.isoenen_US
dc.publisherMIT Digital Computer Laboratoryen_US
dc.relation.ispartofseriesMIT DIC 6889en_US
dc.relation.ispartofseriesProject Whirlwind Memo M-2219en_US
dc.relation.ispartofseriesProject Whirlwind Collection, MC665en_US
dc.titleTesting of Individual Cores in MTC Memory Planesen_US
dc.typeTechnical Reporten_US


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