Now showing items 1610-1629 of 1719

    • T.I.R. release of operational specifications and XD-1 equipment specifications 

      Dodd, S. H. (Lincoln Laboratory - Division 6, 1955-07-28)
      Technical Information Releases were used for equipment specifications and operational specifications for both the prototype and production machines.
    • Tentative Cathode Estimates for 256²x33 and 128²x33 Core Memories 

      Canty, W. J.; Mitchell, J. L. (Lincoln Laboratory - Division 6, 1954-08-06)
      The largest number of cathodes for a 256²x33 memory and 128²x33 memory is estimated to be 4756 and 1912 respectively.
    • Termination of E-Series Reports 

      Rathbone, R. R. (Lincoln Laboratory - Division 6, 1953-07-28)
      The E-series report has been cancelled. All short, informal reports will now be issued as M-series reports. Internal distribution will be assigned by the author.
    • Test planning, concurrence, and conduct in the SAGE system 

      Watt, C. W.; Davis, R.; Proehle, E. C. (Lincoln Laboratory - Division 6, 1955-08-31)
      The logical steps necessary to the planning and execution of SAGE subsystem and system tests are outlined and the various kinds of these tests are defined.
    • Test program for 1954 Cape Cod System 

      Boehmer, Howard W.; Wieser, C. Robert (Lincoln Laboratory - Division 6, 1955-07-28)
      In the letter from the SAGE Test Committee, Subject: Coordination Direction of 1954 Cape Cod System, 29 June 1955, the suggestion was made that planning, maintenance, operation and evaluation in the 1954 Cape Cod System ...
    • Test Results on the DCL Memory Plane 

      Guditz, E. A. (Lincoln Laboratory - Division 6, 1954-05-28)
      The DCL plane (C25) is compared with a standard MTC plane which has General Ceramics cores. Except for requiring slightly higher driving currents for maximum output, the DCL plane compares favorably with the MTC planes and ...
    • Testing Cores for WWII 

      McCusker, J. H. (MIT Digital Computer Laboratory, 1953-03-30)
      Since approximately one to two tests per second have to be made to test sufficient cores for WWII in thirteen weeks, the present testing technique is unfeasible. Semi-automatic or preferably completely automatic testing ...
    • Testing of Individual Cores in MTC Memory Planes 

      Hughes, A. D. (MIT Digital Computer Laboratory, 1953-06-16)
      The 32 x 32 magnetic-core memory planes for MTC were constructed from cores tested and sorted on a production basis. To obviate the possibility of defective cores, each core was retested after it had been wired into a ...
    • Testing of Metallic Cores 

      Hughes, Arthur D. (MIT Digital Computer Laboratory, 1953-01-07)
      Of 668 metallic cores tested, 38.8 percent were selected as good cores. The specification for a good core were: (1) an absence of disturb sensitivity,* (2) a switching time of 7.6 to 9.3 microseconds and (3) a disturbed-one ...
    • Testing the Magnetic-Core Memory System in a Computer 

      Widrow, B. (Lincoln Laboratory - Division 6, 1953-09-18)
      A working memory has a "safe" operating region in a multidimensional space whose coordinates consist of the significant operating parameters of the memory. Errors occur only with excursions of the operating point outside ...
    • A Theory of Deviation from Close Packing in Hexagonal Metal Crystals 

      Goodenough, John B. (MIT Digital Computer Laboratory, 1952-09-11)
      A mechanism is proposed to show how the Fermi surface interacts with the Brillouin zone boundaries. The direction and relative magnitude of the variation of the c/a ratio for hexagonal crystals from the ideal value for ...
    • A Theory of Perovskite-Type Manganites (La,M(II))MnO₃ 

      Goodenough, John B. (Lincoln Laboratory - Division 6, 1954-11-30)
      Semicovalence and its effects on indirect magnetic-exchange interaction are reviewed and applied to the manganites. These considerations lead to qualitative predictions which are in complete accord with the following ...
    • Thesis Proposals and Progress Reports 

      Forrester, Jay W. (MIT Servomechanisms Laboratory, 1948-03-08)
      Memorandum on organization of thesis proposals and progress reports created by MIT Servomechanisms Laboratory research teams.
    • Third Meeting on Air Defense Computer, Nov. 7, 1951 

      Morriss, B. E. (MIT Digital Computer Laboratory, 1951-11-07)
      Memorandum on the third of a series of meetings of Digital Computer Laboratory research staff on the development of an Air Defense Computer.
    • Thoughts on Incremental Permeability 

      Goodenough, John B. (Lincoln Laboratory - Division 6, 1954-09-17)
      After a short discussion of the factors which influence the incremental permeability, three different methods are discussed which should give a large change in incremental permeability with a change of the biasing field. ...
    • Time Schedule for WWII Computer 

      Taylor, Norman H.; Mayer, Rollin P. (MIT Digital Computer Laboratory, 1952-03-25)
      Memorandum outlining the plan to obtain a WWII computer in the minimum amount of time and gives the dates on which certain decisions must be reached.
    • Time schedule for XD-1 machine specifications and evaluation reports 

      Forrester, Jay W. (Lincoln Laboratory - Division 6, 1955-02-07)
      Memorandum providing a time schedule for machine evaluation tests of XD-1.
    • Transformer Drive for a Coincident-Current Magnetic Memory 

      Gates, Earle K. (MIT Digital Computer Laboratory, 1954-01-05)
      Master's Thesis Proposal: Transformer Drive for a Coincident-Current Magnetic Memory.
    • Transients for cryotron tree switch 

      Epstein, Marvin. (Lincoln Laboratory - Division 6, 1956-03-30)
      Describes a cryotron tree switch, the initial conditions for the various transients, and the circuit parameter value. A simple method for calculating the pole zero pattern is found. Finally, an asymptotic expression is ...
    • Transistor circuits for driving coincident current memories. 

      Olsen, Kenneth H. (Lincoln Laboratory - Division 6, 1955-01-21)
      Memorandum discussing transistors and how they are made to pass large currents as needed in magnetic memories by turning off the currents while the transistors are being switched.