dc.contributor.author | Best, R. L. | en_US |
dc.contributor.author | Meisling, T. H. | en_US |
dc.date.accessioned | 2009-06-15T20:33:23Z | |
dc.date.available | 2009-06-15T20:33:23Z | |
dc.date.issued | 1956-03-08 | en_US |
dc.identifier | MC665_r16_M-4218 | en_US |
dc.identifier.uri | http://hdl.handle.net/1721.3/40661 | |
dc.description | Includes: introduction, principle of operation, register selection switch, and figures. | en_US |
dc.description.abstract | A proposed core memory is described that has sequential
access to 256 registers (word storage locations), can read out a new word every 3 microsecond and has word length of 58 bits. A read-rewrite cycle for a given storage location requires 6 microseconds; the rewrite (or write), is accomplished during the 3 microsecond period that the next storage location is being read. Direct storage location selection provides a 3-to-1 selection ratio. Small, low-coercive-force cores are used (0.047 in. O.D., F398, DCL-5-19S-1). Since currents required are small, transistors can be used instead of tubes. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Lincoln Laboratory - Division 6 | en_US |
dc.relation.ispartofseries | Division 6 Memo M-4218 | en_US |
dc.relation.ispartofseries | Project Whirlwind Collection, MC665 | en_US |
dc.subject.other | waveforms | en_US |
dc.subject.other | memory drive lines | en_US |
dc.subject.other | memory address register | en_US |
dc.subject.other | net selection current | en_US |
dc.title | A sequential-access three-microsecond core memory | en_US |
dc.type | Technical Report | en_US |