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dc.contributor.authorTaylor, Norman H.en_US
dc.contributor.authorHosier, W. A.en_US
dc.contributor.authorOlsen, K. H.en_US
dc.date.accessioned2009-05-08T05:18:43Z
dc.date.available2009-05-08T05:18:43Z
dc.date.issued1952-11-18en_US
dc.identifierMC665_r05_M-1640-1.pdfen_US
dc.identifier.urihttp://hdl.handle.net/1721.3/39282
dc.descriptionPresent: H. Anderson, R. Best, R. Callahan, J. Crane, D. Eckl, S. Fine, E. Gates, A. Guditz, A. Heineck, W. Hosier, R. Hughes, J. Jacobs, W. Klein, R. Mayer, D. McCann, J. Mitchell, W. Ogden, K. Olsen, W. Papian, R. Pfaff, H. Rising, D. Shansky, N. Taylor, S. Thompson, B. Widrowitz, J. Woolf, R. von Buelow.en_US
dc.description.abstractThis meeting was devoted to a brief survey of present plans for logical design and physical layout of the Memory Test Computer, simply to introduce it to those members of the group not working directly on it.en_US
dc.language.isoenen_US
dc.publisherMIT Digital Computer Laboratoryen_US
dc.relation.ispartofseriesMIT DIC 6889en_US
dc.relation.ispartofseriesProject Whirlwind Memo M-1640-1en_US
dc.relation.ispartofseriesProject Whirlwind Collection, MC665en_US
dc.titleWWII Meeting of September 12, 1952en_US
dc.typeTechnical Reporten_US


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